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| S3CB018/FB018 PRODUCT OVERVIEW 1 PRODUCT OVERVIEW CALMRISC OVERVIEW The S3CB018/FB018 single-chip CMOS microcontroller is designed for high performance using Samsung' s newest 8-bit CPU core, CalmRISC. CalmRISC is an 8-bit low power RISC microcontroller. Its basic architecture follows Harvard style, that is, it has separate program memory and data memory. Both instruction and data can be fetched simultaneously without causing a stall, using separate paths for memory access. Represented below is the top block diagram of the CalmRISC microcontroller. 1-1 PRODUCT OVERVIEW S3CB018/FB018 S3CB018/FB018 OVERVIEW FEATURES SUMMARY CPU * 8-Bit Serial I/O Interface * * * * 8-Bit RISC architecture 8-bit transmit/receive mode 8-bit receive mode LSB first or MSB first transmission selectable Internal and external clock source Memory * * ROM: 4 Kword (8 K-byte) RAM: 3072 (1024+2048) byte 1024 (X-memory) byte 2048 (Y-memory) byte 16-Bit Serial I/O Interface * * 16-bit transmit/receive mode External clock source Stack * size: maximum 16 (word)-level Coprocessor * * * 26 I/O Pins * MAC 816 8 x 16, 16 x 16 Multiply and Accumulation Arithmetic operation I/O: 26 pins, including 8 S/W open drain pins 8-Bit Basic Timer * * Programmable interval timer 8 kinds of clock source Two Power-Down Modes * * Idle mode: only CPU clock stop Stop mode: selected system clock and CPU clock stop Watchdog Timer * System reset when 11-bit counter overflows Oscillation Sources * * 16-Bit Timer/Counter * * Programmable interval timer Two 8-bit timer counter mode and one 16-bit timer counter mode, selectable by S/W Crystal and Ceramic (0.4-20MHz), RC Oscillation Programmable oscillation source Instruction Execution Times Watch Timer * * * * 50ns at 20MHz for 1 cycle instruction 100ns at 20MHz for 2 cycle instruction Real time clock or interval time measurement Four frequency outputs for buzzer sound 1-2 S3CB018/FB018 PRODUCT OVERVIEW 20 PA[19:0] PD[15:0] Program Memory Address Generation Unit PC[19:0] 20 8 8 HS[0] Hardware Stack TBH DO[7:0] ABUS[7:0] BBUS[7:0] DI[7:0] ALUL ALUR R0 R1 R2 ALU Flag RBUS R3 GPR TBL HS[15] SR1 ILX Data Memory Address Generation Unit Bank 0,1 ILH SR0 ILL IDL0 DA[15:0] IDH IDL1 SPR Figure 1-1. Top Block Diagram of CalmRISC 1-3 PRODUCT OVERVIEW S3CB018/FB018 The CalmRISC building blocks consist of: -- An 8-bit ALU -- 16 general purpose registers (GPR) -- 11 special purpose registers (SPR) -- 16-level hardware stack -- Program memory address generation unit -- Data memory address generation unit 16 GPR' s are grouped into four banks (Bank0 to Bank3) and each bank has four 8-bit registers (R0, R1, R2, and R3). SPR' s, designed for special purposes, include status registers, link registers for branch-link instructions, and data memory index registers. The data memory address generation unit provides the data memory address (denoted as DA[15:0] in the top block diagram) for a data memory access instruction. Data memory contents are accessed through DI[7:0] for read operations and DO[7:0] for write operations. The program memory address generation unit contains a program counter, PC[19:0], and supplies the program memory address through PA[19:0] and fetches the corresponding instruction through PD[15:0] as the result of the program memory access. CalmRISC has a 16-level hardware stack for low power stack operations as well as a temporary storage area. CalmRISC has a 3-stage pipeline as described below: Instruction Fetch (IF) Instruction Decode/ Data Memory Access (ID/MEM) Execution/Writeback (EXE/WB) Figure 1-2. CalmRISC Pipeline Diagram As can be seen in the pipeline scheme, CalmRISC adopts a register-memory instruction set. In other words, data memory where R is a GPR, can be one operand of an ALU instruction as shown below: The first stage (or cycle) is Instruction Fetch stage (IF for short), where the instruction pointed to by the program counter, PC[19:0] , is read into the Instruction Register (IR for short). The second stage is Instruction Decode and Data Memory Access stage (ID/MEM for short), where the fetched instruction (stored in IR) is decoded and data memory access is performed, if necessary. The final stage is Execute and Write-back stage (EXE/WB), where the required ALU operation is executed and the result is written back into the destination registers. Since CalmRISC instructions are pipelined, the next instruction fetch is not postponed until the current instruction is completely finished, but is performed immediately after the current instruction fetch is done. The pipeline stream of instructions is illustrated in the following diagram. 1-4 S3CB018/FB018 PRODUCT OVERVIEW /1 IF /2 ID/MEM EXE/WB IF /3 ID/MEM EXE/WB IF /4 ID/MEM EXE/WB IF IF /5 ID/MEM EXE/WB IF /6 ID/MEM EXE/WB IF ID/MEM EXE/WB Figure 1-3. CalmRISC Pipeline Stream Diagram Most CalmRISC instructions are 1-word instructions, while same branch instructions such as "LCALL" and "LJT" instructions are 2-word instructions. In Figure 1-3, the instruction, I4, is a long branch instruction and it takes two clock cycles to fetch the instruction. As indicated in the pipeline stream, the number of clocks per instruction (CPI) is 1 except for long branches, which take 2 clock cycles per instruction. 1-5 PRODUCT OVERVIEW S3CB018/FB018 OSC Control WT BT/WDT P3.0 - P3.1 Port 3 CalmRISC CPU SIO SI S0 SCK P2.0 - P2.7 Port 2 Timer A TACLK TAOUT P1.0 - P1.7 Port 1 X-Memory 1024 Byte Y-Memory 2048 Byte Control Register 128 Byte (38 Byte) Timer B TBCLK TBOUT P0.0 - P0.7 Port 0 MAC 816 SIO ADDA Figure 1-4. S3CB018/FB018 Block Diagram 1-6 S3CB018/FB018 PRODUCT OVERVIEW PIN ASSIGNMENTS VSS XOUT XIN TEST SI/P0.0 SO/P0.1 RESET SCK/P0.2 BUZ/P0.3 CSI/P0.4 CSO/P0.5 CSCK/P0.6 CFSYNC/P0.7 P1.0 P1.1 P1.7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 S3CB018 32-SOP (Top-View) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD P3.1/SCLK/INT01 P3.0/SDAT/INT00 P2.7/TACLK P2.6/TBOUT P2.5/TBCLK P2.4/TAOUT P2.3/INT13 P2.2/INT12 P2.1/INT11 P2.0/INT10 P1.2 P1.3 P1.4 P1.5 P1.6 Figure 1-5. 32-SOP Pin Assignment VSS XOUT XIN TEST SI/P0.0 SO/P0.1 RESET SCK/P0.2 BUZ/P0.3 CSI/P0.4 CSO/P0.5 CSCK/P0.6 CFSYNC/P0.7 P1.0 P1.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S3CB018 30-SDIP (Top View) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VDD P3.1/SCLK/INT01 P3.0/SDAT/INT00 P2.7/TACLK P2.6/TBOUT P2.5/TBCLK P2.4/TAOUT P2.3/INT13 P2.2/INT12 P2.1/INT11 P2.0/INT10 P1.2 P1.3 P1.4 P1.5 Figure 1-6. 30-SDIP Pin Assignment 1-7 PRODUCT OVERVIEW S3CB018/FB018 I/O PIN DESCRIPTION Table 1-1. S3CB018/FB018 Pin Descriptions (32-SOP) Pin Name P0.0-P0.7 Pin Type I/O Pin Description I/O port with bit programmable pins; Input and output mode are selectable by software; Software assignable pull-up. P0.4-P0.7 can be used as inputs for comparator input CIN0-CIN3.; Alternately they can be used as SI, SO, SCK, BUZ, CSI, CSO, CSCK, CFSYNC. Output port with bit programmable pins; Push-pull output mode and open-drain output mode are selected by software; Software assignable pull-up. I/O port with bit programmable pins; Input and output mode are selectable by software; Software assignable pull-up; P2.0-P2.3 can be used as inputs for external interrupts INT10-INT13. (with noise filter) ; Alternately they can be used as TAOUT, TACLK or TBOUT, TBCLK. I/O port with bit programmable pins; Input or output mode selected by software; software assignable pull-up; P3.0-P3.1 can be used as inputs for external interrupts INT00-INT01. (with noise filter and interrupt polarity control) Table 1-2. S3CB018/FB018 Pin Descriptions (30-SDIP) Pin Name P0.0-P0.7 Pin Type I/O Pin Description I/O port with bit programmable pins; Input and output mode are selectable by software; Software assignable pull-up. P0.4-P0.7 can be used as SI, SO, SCK, BUZ, CSI, CSO, CSCK, CFSYNC, Alternately. O port with bit programmable pins; Push-pull output mode and open-drain output mode are selected by software; Software assignable pull-up. I/O port with bit programmable pins; Input and output mode are selectable by software; Software assignable pull-up; P2.0-P2.3 can be used as inputs for external interrupts INT10-INT13. (with noise filter); Alternately they can be used as TAOUT, TACLK or TBOUT, TBCLK. I/O port with bit programmable pins; Input or output mode selected by software; software assignable pull-up; P3.0-P3.1 can be used as inputs for external interrupts INT00-INT01. (with noise filter and interrupt polarity control) Circuit Type D-2 F-10 Share Pins SI, SO, SCK BUZ, CSI, CSO, CSCK, CFSYNC Circuit Type D-2 F-10 Share Pins SI, SO, SCK BUZ, CSI, CSO, CSCK, CFSYNC P1.0-P1.7 O E-2 P2.0-P2.7 I/O D-4 D-2 INT10-INT13 TAOUT TACLK TBOUT TBCLK INT00-INT01 P3.0-P3.1 I/O D-4 P1.0-P1.5 O E-2 P2.0-P2.7 I/O D-4 D-2 INT10-INT13 TAOUT TACLK TBOUT TBCLK INT00-INT01 P3.0-P3.1 I/O D-4 NOTE: In S3CB018/FB018, the CSI, CSO, CSCK, CFSYNC pins are shared with P0.7-P0.4. 1-8 S3CB018/FB018 PRODUCT OVERVIEW Table 1-3. I/O Pin Description Pin Name CSI CSO CSCK CFSYNC SI SO SCK BUZ INT10-INT13 TAOUT TACLK TBOUT TBCLK INT00-INT01 SDAT SCLK VDD VSS TEST RESET XIN, XOUT Pin Type I O I I I/O I/O I/O I/O I I/O I/O I/O I/O I I I - - - I - AD/DA Serial Input (from codec) AD/DA Serial Output (to codec) AD/DA Serial Clock (from codec) AD/DA Sync signal (from codec) Serial data input Serial data output Serial I/O interface clock signal 0.5 kHz, 1 kHz, 2 kHz, or 4 kHz frequency output at 4.19 MHz for buzzer sound External interrupts. Stop release. Can' t be masked by S/W individually but wholly. Timer A interval mode output Timer A counter external clock input Timer B interval mode output Timer B counter external clock input External interrupts. Stop release. Can be masked by S/W individually. Serial data for Programmable memory Serial clock for Programmable memory Power supply Ground Test signal input Reset signal Crystal, ceramic and RC oscillator signal for system clock (For external clock input, use XIN and input XIN's reverse phase to XOUT) Description 1-9 PRODUCT OVERVIEW S3CB018/FB018 PIN ASSIGNMENTS XDA3 XDA2 XDA1 XDA0 VDD XD0 XD1 XD2 XD3 GND XD4 XD5 XD6 XD7 VDD XD8 XD9 XD10 GND XD11 XD12 XD13 XD14 XD15 VDD/VDDI CSNXH CSNXL WENX OENX GND CSNWIO CSNBIO EVENIO WENIO OENIO VDD CSIN CSCLK CFSYNC CSOUT 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 P0.0 P0.1 P0.2 VDD P0.3 P0.4 P0.5 GND P0.6 P0.7 VDD P1.0 P1.1 P1.2 P1.3 GND P1.4 P1.5 P1.6 P1.7 GND XIN XOUT VDDI/VDD P2.0 P2.1 P2.2 VDD P2.3 P2.4 GND P2.5 P2.6 P2.7 VDD P3.0 P3.1 GND TMODE PIN_RESB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 S3EB010 160-QFP (Top-View) 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 XDA4 XDA5 XDA6 GND XDA7 XDA8 XDA9 VDD/VDDI XDA10 XDA11 XDA12 XDA13 GND TEST PA0 PA1 PA2 VDD/VDDI PA3 PA4 PA5 GND PA6 PA7 VDD PA8 PA9 PA10 PA11 GND PA12 PA13 PA14 PA15 VDD PA16 PA17 PA18 PA19 BKREQX 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 ICLKO GND PD0 PD1 PD2 PD3 GND PD4 PD5 PD6 PD7 VDD/VDDI PD8 PD9 PD10 GND PD11 PD12 PD13 VDD/VDDI PD14 PD15 GND NP64KW XDOCNT DOCNTX OUTDIS VDD RUNST NPMCS NPMOE NPMWE GND PTDO_TXD PTDI_RXD PTMS PTCK_MCLK VDD/VDDI PNTRST_STATEINIT JTAGSEL Figure 1-7. S3EB010 Pin Diagram 1-10 S3CB018/FB018 PRODUCT OVERVIEW Table 1-4. Evaluation Chip Pin Descriptions No. 1-3 5-9 12-15 17-20 22 23 25-27 29, 30 32, 34 36, 37 39 40 41 42 44 45 46 47 49 50 51 52 54 55 56 57 59, 60 62-64 66-68 70-73 75-78 Pin Name P0.0-P0.2 P0.3-P0.7 P1.0-P1.3 P1.4-P1.7 XIN XOUT P2.0-P2.2 P2.3, P2.4 P2.5-P2.7 P3.0, P3.1 TMODE PIN_RESB JTAGSEL PNTRST_STSTEINI T PTCK_MCLK PTMS PTDI_RXD PTDO_TXD NPMWE NPMOE NPMCS RUNST OUTDIS DOCNTX XDOCNTX NPM64KW PD15-PD14 PD13-PD11 PD10-PD8 PD7-PD4 PD3-PD0 I/O I I I I I I I O O O O O I I I I I/O Port 3 Test Mode pin; 1: skip warm-up time, 0: normal mode Asynchronous reset, active low JTAG mode select; 1: parallel, 0: serial JTAG/UART pin JTAG/UART pin JTAG/UART pin JTAG/UART pin JTAG/UART pin Program Memory Write Enable, active low Program Memory Output Enable, active low Program Memory Chip Select, active low Run Status Indicator I/O PAD Disable for debugger Data Bus Output Control External X-Memory Data Bus Output Control Up to 64KW Program Memory, active low Program Memory Data Bus I O I/O Clock In Clock Out Port 2 O Port 1 Pin Type I/O Port 0 Description 1-11 PRODUCT OVERVIEW S3CB018/FB018 Table 1-4. Evaluation Chip Pin Descriptions (Continued) No. 80 81 82-85 87-90 92-95 97, 98 100-102 104-106 107 109-112 114-116 118-124 126-129 131-134 136-138 140-144 146 147 148 149 151 152 153 154 155 157 158 159 160 VDD GND Pin Name ICLKO BKREQX PA19-PA16 PA15-PA12 PA11-PA8 PA7, PA6 PA5-PA3 PA2-PA0 TEST XDA13-XDA10 XDA9-XDA7 XDA6-XDA0 XD0-XD3 XD4-XD7 XD8-XD10 XD11-XD15 CSNXH CSNXL WENX OENX CSNWIO CSNBIO EVENIO WENIO OENIO CSIN CSCLK CFSYNC CSOUT Power supply Ground O O O O O O O O O I I I O - - External X-Memory High Byte Chip Select, active low External X-Memory Low Byte Chip Select, active low External X-Memory Write Enable, active low External X-Memory Output Enable, active low External I/O Word Chip Select, active low External I/O Byte Chip Select, active low External I/O Even Indicator; 1:Even, 0: Odd External I/O Write Enable, active low External I/O Output Enable, active low AD / DA Serial Input (from codec) AD / DA Serial Clock (from codec) AD / DA Sync signal (from codec) AD / DA Serial Output (to codec) 4, 11, 24, 28, 35, 43, 53, 61, 69, 86, 96, 103, 113 125, 135, 145, 156 8, 16, 21, 31, 38, 48, 58, 65, 74, 79, 91, 99, 108, 117 130, 139, 150 I/O External X-Memory Data Bus I O Test pin for debugger External X-Memory Address Pin Type O I O ICLK Output Break input for debugger Program Memory Address Description 1-12 S3CB018/FB018 PRODUCT OVERVIEW PIN CIRCUIT DIAGRAMS VDD VDD Pull-Up Resistor In Output Disable Schmitt Trigger Pull-up Enable Data P-Channel Circuit Type C I/O Figure 1-8. Pin Circuit Type B (RESET) Figure 1-10. Pin Circuit Type D-2 (P0.0-P0.3, P2.4-P2.7) VDD VDD Pull-up Enable P-Channel Out Data Output Disable P-Channel Circuit Type C Data I/O Output Disable N-Channel Noise Filter Schmitt Trigger Input Ext. INT Figure 1-9. Pin Circuit Type C Figure 1-11. Pin Circuit Type D-4 (P2.0-P2.3, P3) 1-13 PRODUCT OVERVIEW S3CB018/FB018 VDD VDD Open-drain Enable Data Pull-up Enable P-Channel Out N-Channel Data Output Disable Comparator Enable Circuit Type C I/O Input Reserved Figure 1-12. Pin Circuit Type E-2 (P1) Figure 1-13. Pin Circuit Type F-10 (P0.4-P0.7) 1-14 S3CB018/FB018 ELECTRICAL DATA 18 OVERVIEW (TA = 25C) Parameter Supply voltage Input voltage Output voltage Output current high Output current low Operating temperature Storage temperature ELECTRICAL DATA Table 18-1. Absolute Maximum Ratings Symbol VDD VI VO I OH I OL TA TSTG Conditions - - - One I/O pin active All I/O pins active One I/O pin active Total pin current for ports 1, 2, 3 - - Rating - 0.3 to + 6.0 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 18 - 60 + 30 + 100 - 40 to + 85 - 65 to + 150 Unit V mA C Table 18-2. D.C. Electrical Characteristics (TA = - 40C to + 85C, VDD = 1.8 V to 5.5 V) Parameter Operating Voltage (HSX mode) FCPU = 3 MHz Operating Voltage (MSX mode) FCPU = 3 MHz 1.8 5.5 VDD FCPU = 10 MHz 1.8 4.5 - 5.5 5.5 Symbol VDD Conditions FCPU = 20 MHz Min 4.5 Typ - Max 5.5 Unit V 18-1 ELECTRICAL DATA S3C (TA = 40 C, V = 1.8 V to 5.5 V) Conditions Min 0.8 V - Max DD Parameter VIH1 X Unit V IH2 IH2 VDD- 0.1 - - 0.2 VDD 0.1 VDD-1.0 - - - 2 2 - - 3 20 - - -3 -20 - - 510 - - 710 3 -3 910 k uA uA V Input low voltage VIL1 VIL2 All input pins except VIL2 XIN VDD = 5V; IOH = -1 mA All output pins VDD = 5V; IOL = 8 mA All output pins except VOL2 VDD = 5V; IOL = 15 mA, Port 1 VIN = VDD All input pins except ILIH2 VIN = VDD XIN, XTIN VIN = 0 V All input pins except ILIL2 VIN = 0 V XIN, XTIN, RESET VOUT = VDD All I/O pins and Output pins VOUT = 0 V All I/O pins and Output pins VDD = 5.0 V, TA = 25C, XIN = VDD, XOUT = 0V VDD = 5.0 V,TA = 25C, XIN = VDD, XOUT = 0V VDD = 5.0 V, TA = 25C, XIN = VDD, XOUT = 0V VIN = 0 V; VDD = 5 V 10% Ports 0,1,2,3,4,5 VIN = 0 V; VDD = 5 V 10% TA=25C Output high voltage Output low voltage VOH1 VOL1 VOL2 Input high leakage current ILIH1 ILIH2 Input low leakage current ILIL1 ILIL2 Output high leakage current Output low leakage current Oscillator feed back resistors ILOH ILOL Rosc1 (HSX) Rosc2 (MSX) 510 710 910 Rosc3 (LSX) 2.0 2.7 3.5 M Pull-up resistor RL1 RL2 30 50 70 k 110 210 310 TA=25C, RESET only 18-2 S3CB018/FB018 ELECTRICAL DATA Table 18-2. D.C. Electrical Characteristics (Continued) (TA = - 40C to + 85C, VDD = 1.8 V to 5.5 V) Parameter Supply current (1) Symbol IDD1(2) Conditions Operating mode: VDD = 5 V 10% 20 MHz crystal oscillator(HSX) 5 MHz crystal oscillator(MSX) VDD = 3 V 10% 5 MHz crystal oscillator(MSX) Min - Typ 10 4 2 Max 20 8 4 5 2 0.8 3 1.2 Unit mA IDD2(3) Idle mode: VDD = 5 V 10% 20 MHz crystal oscillator(HSX) 5 MHz crystal oscillator(MSX) VDD = 3 V 10% 5 MHz crystal oscillator(MSX) - 2.5 1 0.4 mA IDD3 Stop mode VDD = 5 V 10% VDD = 3 V 10% - 0.5 0.2 uA NOTES: 1. Supply current does not include current drawn through internal pull-up resistors or external output current loads. 2. In operating current test mode Timer A and Timer B are running. 3. In idle current test mode the Watch timer is running. 4. The operating and idle currents are measured at weak mode. Table 18-3. A. C. Electrical Characteristics (TA = -40C to + 85C, VDD = 1.8 V to 5.5 V) Parameter Interrupt input high, low width RESET input low width Symbol tINTH, tINTL tRSL Conditions P2.0 - P2.3, P3.0 - P3.1 VDD = 5V VDD = 5V 10% Min 200 1 Typ - - Max - - Unit ns us NOTE: User must keep a value larger than the min value. 18-3 ELECTRICAL DATA S3CB018/FB018 tINTL tINTH 0.8 VDD 0.2 VDD Figure 18-1. Input Timing for External Interrupts tRSL RESET 0.2 VDD Figure 18-2. Input Timing for RESET 18-4 S3CB018/FB018 ELECTRICAL DATA Table 18-4. Data Retention Supply Voltage in Stop Mode (TA = - 40C to + 85C, VDD = 1.8 V to 5.5V) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR VDDDR = 1.5V Conditions Min 1.5 - Typ - - Max 5.5 2 Unit V A NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads. RESET Occur Stop Mode Data Retention Mode Oscillation Stabilization Time Normal Operating Mode ~ ~ ~ ~ VDD VDDDR Execution of STOP Instruction RESET 0.2VDD tWAIT NOTE: tWAIT is the same as 2048 x 32 x 1/fxx Figure 18-3. Stop Mode Release Timing When Initiated by a RESET 18-5 ELECTRICAL DATA S3CB018/FB018 Osc Start up time Oscillation Stabilization Time Stop Mode Data Retention Normal Operating Mode ~ ~ ~ ~ VDD VDDDR Execution of STOP Instruction INT 0.2VDD tWAIT NOTE: tWAIT is the same as 2048 x 32 x 1/fxx. The value of 2048 which is selected for the clock source of the basic timer counter can be changed. Then the value of tWAIT will be changed and ,when you select 16 instead of 32, the value of twait will also be changed. Figure 18-4. Stop Mode Release Timing When Initiated by Interrupts 18-6 S3CB018/FB018 ELECTRICAL DATA Table 18-5. Synchronous SIO Electrical Characteristics (TA = - 40C to + 85C VDD = 4.5 V to 5.5 V, VSS = 0 V, fxx = 10 MHz oscillator ) Parameter SCK Cycle time Serial Clock High Width Serial Clock Low Width Serial Output data delay time Serial Input data setup time Serial Input data Hold time Symbol tCYC tSCKH tSCKL tOD tID tIH Conditions - - - - - - Min 200 60 60 - 40 100 Typ - - - - - - Max - - - 50 - - Unit ns tCYC tSCKL SCK 0.8 VDD 0.2 VDD tID tIH 0.8 VDD SI Input Data 0.2 VDD tOD tSCKH SO Output Data Figure 18-5. Serial Data Transfer Timing 18-7 ELECTRICAL DATA S3CB018/FB018 Table 18-6. Main Oscillator Frequency (TA = -40C + 85C, VDD = 1.8 V to 5.5 V) Oscillator Crystal Clock Circuit XIN XOUT Test Condition LSX mode Min 32 Typ 32.768 Max 35 Unit kHz C1 C2 MSX mode HSX mode Ceramic XIN XOUT 0.4 0.4 32 - - 32.768 10 20 35 MHz LSX mode kHz C1 C2 MSX mode HSX mode External clock XIN XOUT 0.4 0.4 32 - - 32.768 10 20 35 MHz LSX mode kHz MSX mode HSX mode RC r = 22Kohm, VDD = 5 V Direct soldering 0.4 0.4 1.4 - - 2 10 20 2.6 MHz MHz NOTES: 1. Keep the wiring length as short as possible. 2. Do not cross the wiring with the other signal lines. 3. Do not route the wiring near a signal line through which a high fluctuating current flows. 4. Always make the ground point of the oscillator capacitor the same potential as VSS. 5. Do not ground the capacitor to a ground pattern through which a high current flows. 6. Do not fetch signals from the oscillator. 18-8 S3CB018/FB018 ELECTRICAL DATA 3000 15K 22K 2000 Frequency [kHz] 1500 30K 33K 36K 62K 1000 82K 120K 180K 500 0 1.8 2V 3V 4V VDD [V] 5V 5.5V 6V 300K 2500 Figure 18-6. RC Oscillator Characteristic Curve 18-9 ELECTRICAL DATA S3CB018/FB018 Table 18-7. Main Oscillator Oscillation Stabilization Time (tST1) (TA = -40C + 85C, VDD = 4.5 V to 5.5 V) Oscillator HSX Crystal Ceramic External clock MSX Crystal Ceramic External clock LSX 32768Hz Crystal release. Test Condition(Normal mode) VDD = minimum oscillation voltage range. Min - - Typ - - - - - - 200 Max 10 4 - 100 50 - 500 Unit ms ms ns ms ms ns ms XIN input high and low level width (tXH, tXL) VDD = minimum oscillation voltage range. 50 - - XIN input high and low level width (tXH, tXL) VDD = minimum oscillation voltage range. 50 - NOTE: Oscillation stabilization time (tST1) is the time that is required to stabilize oscillation after a reset or STOP mode 1/fosc1 tXL tXH XIN VDD - 0.1 V 0.1 V Figure 18-7. Clock Timing Measurement at XIN 18-10 S3CB018/FB018 ELECTRICAL DATA fCPU 20 MHz B 10 MHZ A 3 MHZ 0.4 MHz 1 2 1.8 3 4 4.5 Supply Voltage (V) Minimum instruction clock = 1/1 x oscillator frequency 5 5.5 6 7 Figure 18-8. HSX Mode Operating Voltage Range fCPU 10 MHz B A 3 MHZ 0.4 MHz 1 2 1.8 3 4 4.5 Supply Voltage (V) Minimum instruction clock = 1/1 x oscillator frequency 5 5.5 6 7 Figure 18-9. MSX Mode Operating Voltage Range 18-11 S3CB018/FB018 MECHANICAL DATA 19 OVERVIEW #30 MECHANICAL DATA The S3CB018/FB018 is available in a 30-pin SDIP package (Samsung: 30-SDIP-400) and a 32-pin SOP package (32-SOP-450A). Package dimensions are shown in Figures 20-1 and 20-2. #16 0-15 0.2 8.94 #1 #15 27.88MAX 27.48 0.2 0.1 0.1 0.51 MIN 0.56 (1.30) 1.12 1.778 NOTE: Dimensions are in millimeters. Figure 19-1. 30-Pin SDIP Package Dimensions 3.30 0.3 5.08 MAX 3.81 0.2 0.2 5 +0 - 0 .1 .05 30-SDIP-400 10.16 19-1 MECHANICAL DATA S3CB018/FB018 #32 #17 12.00 0.3 0.2 2.40 MAX #1 19.90 0.2 #16 0.2 0.20 + 0.1 - 0.05 (0.43) 0.40 0.1 1.27 NOTE: Dimensions are in millimeters Figure 19-2. 32-SOP-450A Package Dimensions 19-2 0.05 MIN 2.00 0.78 0.2 32-SOP-450A 8.34 11.43 0-8 S3CB018/FB018 S3FB018 20 OVERVIEW S3FB018 FLASH MCU The S3FB018 single-chip CMOS microcontroller is the FLASH version of the S3CB018 microcontroller. It has an on-chip FLASH ROM instead of masked ROM. The FLASH ROM is accessed in serial data format. The S3FB018 is fully compatible with the S3CB018, both in function and in pin configuration. Because of its simple programming requirements, the S3FB018 is ideal for use as an evaluation chip for the S3CB018. 20-1 S3FB018 S3CB018/FB018 PIN ASSIGNMENTS VSS XOUT XIN VPP/TEST SI/P0.0 SO/P0.1 RESET/RESET SCK/P0.2 BUZ/P0.3 CSI/P0.4 CSO/P0.5 CSCK/P0.6 CFSYNC/P0.7 P1.0 P1.1 P1.7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 S3FB018 32-SOP (Top-View) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD P3.1/INT01/SCLK P3.0/INT00/SDAT P2.7/TACLK P2.6/TBOUT P2.5/TBCLK P2.4/TAOUT P2.3/INT13 P2.2/INT12 P2.1/INT11 P2.0/INT10 P1.2 P1.3 P1.4 P1.5 P1.6 Figure 20-1. 32-SOP Pin Assignment VSS XOUT XIN VPP/TEST SI/P0.0 SO/P0.1 RESET/RESET SCK/P0.2 BUZ/P0.3 CSI/P0.4 CSO/P0.5 CSCK/P0.6 CFSYNC/P0.7 P1.0 P1.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 S3FB018 30-SDIP (Top View) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VDD P3.1/INT01/SCLK P3.0/INT00/SDAT P2.7/TACLK P2.6/TBOUT P2.5/TBCLK P2.4/TAOUT P2.3/INT13 P2.2/INT12 P2.1/INT11 P2.0/INT10 P1.2 P1.3 P1.4 P1.5 Figure 20-2. 30-SDIP Pin Assignment 20-2 S3CB018/FB018 S3FB018 Table 20-1. Descriptions of Pins Used to Read/Write the FLASH ROM Main Chip Pin Name P3.0 Pin Name SDAT Pin No. 30(28) During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/pushpull output port. Serial clock pin. Input only pin. Power supply pin for FLASH ROM cell writing (indicates that FLASH enters into the writing mode). When 12.5 V is applied, FLASH is in writing mode and, when 5 V is applied, FLASH is in the reading mode. When FLASH is operating , hold GND. Chip Initialization Logic power supply pin. VDD should be tied to +5 V during programming. P3.1 TEST SCLK Vpp (TEST) 31(29) 4 I/O I RESET VDD/VSS RESET VDD/VSS 7 32/1(30/1) I - NOTE: Pin No. is for 100 QFP type package. (for 100 TQFP, the pins with the same name have same functions). Table 20-2. Comparison of S3FB018 and S3CB018 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration FLASH ROM Programmability S3FB519 4K word (8K byte) FLASH ROM 1.8 V to 5.5 V VDD = 5 V, VPP (TEST) = 12.5 V 32-SOP/30-SDIP User programmable 32-SOP/30-SDIP Programmed at the factory S3CB519 4K word (8K byte) FLASH ROM 1.8 V to 5.5 V 20-3 S3FB018 S3CB018/FB018 Table 20-3. Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Input voltage Output voltage Output current high Output current low Operating temperature Storage temperature TA TSTG I OL Symbol VDD VI VO I OH One I/O pin active All I/O pins active One I/O pin active Total pin current for ports 1, 2, 3 - - Conditions - - - Rating - 0.3 to + 6.0 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 18 - 60 + 30 + 100 - 40 to + 85 - 65 to + 150 C Unit V mA Table 20-4. D.C. Electrical Characteristics (TA = - 40C to + 85C, VDD = 1.8 V to 5.5 V) Parameter Operating Voltage (HSX mode) FCPU = 3 MHz Operating Voltage (MSX mode) FCPU = 3 MHz 1.8 5.5 VDD FCPU = 10 MHz 1.8 4.5 - 5.5 5.5 Symbol VDD Conditions FCPU = 20 MHz Min 4.5 Typ - Max 5.5 Unit V 20-4 S3CB018/FB018 S3FB018 Table 20-4. D.C. Electrical Characteristics (Continued) (TA = - 40C to + 85C, VDD = 1.8 V to 5.5 V) Parameter Input high voltage Symbol VIH1 VIH2 Input low voltage VIL1 VIL2 Output high voltage Output low voltage VOH1 VOL1 VOL2 Input high leakage current ILIH1 ILIH2 Input low leakage current ILIL1 ILIL2 Output high leakage current Output low leakage current Oscillator feed back resistors ILOH ILOL Rosc1 (HSX) Conditions All input pins except VIH2 XIN All input pins except VIL2 XIN VDD = 5V; IOH = -1 mA All output pins VDD = 5V; IOL = 8 mA All output pins except VOL2 VDD = 5V; IOL = 15 mA, Port 1 VIN = VDD All input pins except ILIH2 VIN = VDD XIN, XTIN VIN = 0 V All input pins except ILIL2 VIN = 0 V XIN, XTIN, RESET VOUT = VDD All I/O pins and Output pins VOUT = 0 V All I/O pins and Output pins VDD = 5.0 V, TA = 25C XIN = VDD, XOUT = 0V VDD = 5.0 V, TA = 25C XIN = VDD, XOUT = 0V VDD = 5.0 V, TA = 25C XIN = VDD, XOUT = 0V VIN = 0 V; VDD = 5 V 10% Ports 0,1,2,3,4,5 VIN = 0 V; VDD = 5 V 10% TA=25C Min 0.8 VDD VDD- 0.1 - Typ - Max VDD Unit V - 0.2 VDD 0.1 VDD-1.0 - - - - 2 2 V - - 3 20 uA - - -3 -20 - - 510 - - 710 3 -3 910 uA k Rosc2 (MSX) 510 710 910 Rosc3 (LSX) 2.0 2.7 3.5 M Pull-up resistor RL1 RL2 30 50 70 k 110 210 310 TA=25C, RESET only 20-5 S3FB018 S3CB018/FB018 Table 20-4. D.C. Electrical Characteristics (Continued) (TA = - 40C to + 85C, VDD = 1.8 V to 5.5 V) Parameter Supply current (1) Symbol IDD1(2) Conditions Operating mode: VDD = 5 V 10% 20 MHz crystal oscillator(HSX) 5 MHz crystal oscillator(MSX) VDD = 3 V 10% 5 MHz crystal oscillator(MSX) Min - Typ 10 4 2 Max 20 8 4 5 2 0.8 3 1.2 Unit mA IDD2(3) Idle mode: VDD = 5 V 10% 20 MHz crystal oscillator(HSX) 5 MHz crystal oscillator(MSX) VDD = 3 V 10% 5 MHz crystal oscillator(MSX) - 2.5 1 0.4 mA IDD3 Stop mode VDD = 5 V 10% VDD = 3 V 10% - 0.5 0.2 uA NOTES: 1. Supply current does not include current drawn through internal pull-up resistors or external output current loads. 2. In operating current test mode Timer A and Timer B are running. 3. In idle current test mode the Watch timer is running. 4. The operating and idle currents are measured at weak mode. 20-6 |
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